Conclusions And Future Scope Engineering Essay

Conclusions And Future Scope Engineering testifyIn the integrated overlap industry, the ceaseless(prenominal) effort to decrease critical transistor dimensions in some(prenominal)ly new technology guarantees that the prominence of electrostatic streamlet will continue to grow. Devising ways to value electronic crafts against ESD is just as central as determining how to process and manufacture them because a crossway with might to damage will not be accepted. As a result of increasing force of devices to ESD because of miniaturization, the problem of ESD is now being dealt by most IC manufacturers and electronic administration institutioners at several levels, from projecting on-chip shelter gos to off chip security measures design for systems. Once an IC is packaged and shipped to a customer, however, the in-built, on-chip rampart circuit is the only means of defense against ESD damage. At the system level, the on-chip surety may not be sufficient to handle the sys tem level ESD exposure. So off-chip or on- climb on protection devices ar inevitable to protect the system from real world ESD. While circuit designers take aim successfully created robust ESD protection for past technologies, a lack of understanding of entrapuates of ESD on variant devices, circuits and systems the mechanisms underlying ESD damage makes the might of electronic components to ESD still a hot topic of research.Mathematical analytic thinking and estimation to calculate the bring on transient potential drops inshield and un screen cablegrams is presented. This enables us to find the generate potentiality and its rise era appearing at the terminals of the electrical equipment which argon connected to such cables. This enables the designers to design protection circuits at the front-end of the equipment. The effect of ESD on logic gates, one-dimensional circuits, digital circuits, microcontrollers and complex electronics ar presented. This chapter presents the contributions of this thesis toward implementing a methodology of motion picture of the effects of in locate and take ESD on assorted electronic components. Also the implementation of the come on design and protection circuits on a custom designed microcontroller venire based on an understanding of the ESD ill luck mechanisms of various devices and circuits is presented. This chapter covers the future scope on the research work carried out on ESD. The fol wiped out(p)ing results and conclusions have been arrived upon.8.1 Overall ConclusionsMathematical equations have been developed and argon implemented in MATLAB by which the join and induced emfs in unshielded and shielded cables can be cipher.The values of the induced voltages obtained agree with the published results by different authors.For tactual sensation bombardment ESD, graduate(prenominal)er induced voltages are observe upto 10 megacycle per second for CSD, upto 2.5 MHz for propagate out dribble an d in the 20 to 100 MHz range for all the three terminations resistive, RC electrical shunt and CMOS device. The induced voltages are higher in the case of contact send packing compared to air discharge or CSD. The induced voltage in an unshielded cable cast ups with the decrease in the rise time and distance, and increase in the decimal point bounteousness and the damping factor for the CSD occurrent model.The circus tent value of the induced voltage over collect to IEC contact discharge ESD at 8 kV for resistive termination is 625V and 7.8 mV for RC shunt termination. The peak value of the induced voltage referable to IEC air discharge ESD at 16 kV is 6.25 V and 3.25 mV for RC shunt termination. The peak value of the induced voltage at the input of a CMOS device is 14 V for contact discharge and 0.6 V for air discharge. It can be inferred that RC shunt terminations are preferred compared to the resistive or CMOS device termination as the induced voltages are in mV range.In case of shielded cable, a generic program in Visual C++ to visualise the induced voltages for varying parameters of the current waveform, length, height of the cable and angle of incidence has been implemented. This can as well be used to calculate induced voltages for different cable configurations. Using MATLAB, the info imported from Visual C++ is used to calculate induced voltages. The equations developed give the voltages induced whose values are in blind drunk agreement with those published by other authors.The induced voltages are investigated for braided and unbraided shielded cables. The induced voltage and current in the center conductor is larger for a braided cable compared to a non-braided cable. This analysis estimates the transient voltages appearing at the input of the system connected to the shielded cable. This estimate can be used to develop curb mitigation techniques to protect the sensitive system that is connected to the shielded cable. It has been calcul ated by dissimulation that in shielded cables, the voltages induced due to radiated ESD is negligible thereby reinforcing the theory that shielded cables can protect equipment from high frequency radiated fields due to ESD.The effect of variation of the parameters such the cable length, height of the cable above the ground even and the angle of incidence of the ESD pulse has been discussed. The peak amplitude of the cable sheath current decreases correspondingly with decrease in the length of the cable. This change in the concomitant of the peak is due to smaller value of inductance in case of shorter cables as compared to long cables. The peak amplitude of thecable sheath current correspondingly decreases with increase in the height of the cable. The sheath current decreases with the increase in angle of incidence, as the induced current is function of cos i. The induced voltage in turn depends upon sheath current and surface transfer impedance of the cable. The induced voltages for a shielded cable of length 1m, height 0.1m and angle of incidence 30o are 1.4-10-8V for braided and 6.6-10-16V for non braided cable as presented in Table 3.3.Mathematical analysis is used to model the response of Very High relative frequency amplifier to ESD generated radiated EM fields. Using MATLAB the effect of the radiated fields on the induced voltages in a VHF amplifier for various distances from the ESD stem is calculated. It is observed that a greater part of the energy due to ESD simulation currents has frequency components in the range of 200 to 400 MHz extending to the VHF and UHF bands. So the VHF amplifier is susceptible to ESD events in this frequency range. If the distance between the ESD generator and the pickup truck feeler is decreased, the peak magnitude of the voltage coupled to the amplifier input terminals increases. The amplitude of the fields at antenna terminals, open circuit voltage at antenna input terminals, voltage at the input and fruit of t he amplifier decreases sharply with increase in distance from ESD source. It has been observed that the induced voltages at the amplifier input terminals can be as high as7.446 V with a rise time of approximately 1 ns for a distance of 0.5 m between the ESD generator and the pickup antenna as inclined in Table 4.1. This can cause malfunction of the electronic circuitry in spite of appearance the amplifier.The spice circuit modeling with transient analysis concurs with the experimental results for air discharge on elongate circuits. The zero crossing detector built with an opamp is more(prenominal) susceptible to ESD when compared to the RC phase shift oscillator built with distinct components. It is through an experiment verified and the modeling withal revealed that the oscillator circuit using discrete components took some time to adopt back to its initial working condition after the ESD discharge due to the slow discharge of the charges accumulated. In the indirect discharg e it is seen that the ESD effect depends on both distance and discharge voltage. Higher discharge voltage and shorter distances produce larger transients and distortions in analog circuits. Direct air discharge of 15kV at the ZCD input damage the opamp but the oscillator recovered after 750s. Direct air discharge of 15kV at oscillator produce affects the production of oscillator for 1.4ms. The ZCD payoff remains high till the sine wave output of oscillator circuit recovers. The spice modeling in like manner give the same results for discharge at oscillator output.In the radiative coupling the transient appearing on the ZCD output could be due to differential mode and the common mode could not be investigated. In the direct air discharge conducted at the input point of the ZCD circuit, there could be two types of coupling the direct electrical capacity coupling to circuit and near field coupling for the common mode. In this case also the common mode was not investigated, so th e transients shown are only differential mode. In the direct air discharge at oscillator output, the differential mode and common mode transients were seen. But the voltage probes and current probes of high voltage and low rise time of 1ns range with an accuracy of less than 5% were not available. thusly the initial rise time and the maximum amplitude of the transient could not be measured experimentally with good accuracy.The digital switching circuit without decoupling electrical condensers at Vcc malfunctioned when an ESD event occurred at a distance of 35 cm from the circuit. The transient touch on only the entropy stream and the circuit stopped operation. Post discharge analysis revealed that Binary counter IC SN74LS393N had failed functionally (all output pins were malfunctioning). The importance of adding decoupling capacitors to the supply point of to each one of the ICs is verified.Experiments carried out to study the response of entropy to ESD in a digital switching circuit with decoupling capacitors at Vcc reveal that the effect of ESD on the data and clock depends on the position of trigger and also the plane of coupling. During discharge onto the horizontal coupling plane (HCP), the instance of occurrence of the discharge (when Data and Clock are High or Low) played an important role on the effect of ESD on the output data stream. When both data and clock are High, increase in data amplitude or data inversion occurs and also there is increase in the amplitude of clock. The distance at which the pulse is fired onto the HCP reflects on the amplitude of the transient. During discharge onto the vertical coupling plane (VCP) there is a loss of data and transient with more than 50V peak amplitude is introduced. The discharge to VCP affected the digital data more than the discharge to HCP.Experiments are also carried out by varying the values of decoupling capacitors in the digital switching circuit and it is observed that smaller the value of dec oupling capacitor, the more susceptible the circuit becomes to ESD. The decoupling capacitor with higher value of content (0.47F) offered better immunity to ESD in our digital circuit because of its ability to pass only lower frequencies thereby rejecting the high frequency ESD transients.Experimental investigations of the TTL and CMOS logic gates reveal that CMOS devices are more susceptible to ESD than TTL devices due to the presence of a dielectricmedia in CMOS devices which can easily breakdown at high voltages. The output of CMOS logic gates deteriorated after ESD stress and did not recover after determine.It is verified experimentally that the susceptibility of a circuit to ESD in the conflate mode circuit can be greatly trim back by properly grounding it. In the mixed mode circuit used, the data is affected more by transients of various voltages based on the discharge voltage given when the analog and digital drive are common. This reiterates the fact, when the analog an d digital grounds are common the high frequency return paths from the digital ground (astable multivibrator circuit using 555 Timer) reach the analog ground (inverting amplifier using opamp) and affect the output. In the mixed mode circuit used when the analog and digital grounds are separated there are no transients due to ESD in the analog output. Hence separate analog and digital grounds are recommended.Direct air discharge of 12 kV twice on the GPIO pin of the custom designed 8 microprocessor chip microcontroller diagnostic circuit resulted in the impedance of the board becoming very low implying there is a dead short between the VDD and the VSS rails of the microcontroller. The microcontroller shut itself down by modify the thermal shutdown feature. The failure of all the three designed diagnostic tests involving digital ports, UART and PWM channels are observed. It is observed that the failure in the 8-bit microcontroller is through the Vcc and Ground pins when the ESD even t was closer to these pins. This may be because of the capacitor across Vcc and Ground discharging into these pins due to the ESD event. For the ESD event at other pins, mostly malfunction was observed.The MSP430 projectPad with 16 bit microcontroller is quite immune to ESD owing to its inbuilt design and ESD considerations. This is confirmed experimentally by perform indirect and direct ESD tests at specified standard voltages. However direct contact discharge of 8kV given to the Tx-Rx pins of the jumper array resulted in the damage of the communication port of the 16 bit microcontroller MSP 430G2231 IC. The microcontroller MSP 430G2231 is found to be not communicating with the software and the program is not executable. The communication port (Rx-Tx pins) needs protection in the form of TVS diodes.The 8 bit microcontroller system configured to do a diagnostic check of itsfunctioning during an ESD event had no extra on-board protection devices other than the on- chip protection . The 8 bit microcontroller did not stand up the IEC recommended up to 15kV air discharge perhaps because it was designed on a two layer PCB board. The MSP 430 launch pad with the 16 bit microcontroller on a quatern layer PCB was designed keeping in mind the ESD considerations. The 16 bit microcontroller also did not withstand the IECrecommended upto 8kV contact discharge at the communication port perhaps because of lack of extra protection. Continuous discharges on 8 bit microcontroller led to its thermal shutdown. But the continuous discharges on the 16 bit and 32 bit did not result in thermal shutdown perhaps because it was designed on four layer boards.All the observations from the previous tests and conclusions are put to use in the custom designed four layer board with 32 bit microcontroller interfaced with various components like the UART, speech sound interface, USB, LCD display and key matrix. All the standard design rules for PCB design are followed in the custom design ed microcontroller test boards one populated with components having in-built on-chip protection and another board with extra off-chip on-board protection devices.In the custom designed 32 bit microcontroller system on four layer board it is observed that the placement of components on the board and board design played an important role in the systems sturdiness to ESD. The adherence to standard design rules such as split ground and reason planes proper component placement to minimize loop area fountain supply decoupling using ferrite beads and decoupling capacitors placement of connectors, user interfaces and output devices at the edges of the board separating analog and digital sections has made the microcontroller boards quite loaded against ESD. Also the on-board protection devices at strategic locations such as the input/output, data and power points, communication port and at the input points of the interfaces in the custom designed 32 bit microcontroller system plays a vit al role in the robustness of the system.The adherence to standard design rules has made the microcontroller board with components having in-built on-chip protection also quite rigid against ESD. The board with on-chip protection is affected by ESD with problems like malfunction or reset on power on with a change LCD interface module. The other board has extra on-board protection devices like ferrite bead used to isolate the noisy digital section from the analog section, decoupling capacitors for power supply decoupling, schottky diode used for ESD protection of USB and TVS diodes used at input points of microcontroller, LCD display, audio amplifier, UART and USB. The board with extra on-board protection devices has only temporary resets and is hardly affected by ESD, and the interface modules are also functioning normally. So experimentally it has been concluded that with adherence to board design and just in-built, on-chip protection the insurance are mitigated but malfunctions o ccur which only recover on hard reset on power ON whereas with extra on-board protection devices included, the damages are completely eliminated, malfunctions are trim and only temporary reset occurs. It can be concluded that not only standard board design rules need tobe implemented it is also needed to provide on-board protection against ESD by choosing appropriate protection devices and placing them at appropriate and strategic locations like the input pins and supply pins of the device.Experiments of direct air discharge are conducted on the insulators in FPGA/CPLD kit like seven section LED display, LCD and FRC, and contact discharge conducted on the metal points like the switches, pins and the mounting screws. An air discharge of 8 kV on Liquid Crystal Display distorts the data but resets with power ON and an air discharge of 15kV damages the data on the LCD which cannot be restored on reset. An air discharge of 2kV and 4kV had no effect whereas an air discharge of 8 kV and 15 kV distorted the output on seven segment LED display but the display reset to normal with power ON. A contact discharge of 2 kV and 4kV on the HEX keys feeding the data to seven segment display had no effect but a contact discharge of 8 kV shorted the keys which in turn displayed wrong display data. All these devices had only on-chip protection by the manufacturer and these devices needed off-chip, on-board protection devices to make them less susceptible to ESD.Huge transients are observed when air discharge is carried out on the FRC cables connected to the DAC module. When a contact discharge of 2 kV is given on the input pin 187 of the mother mopboard the DAC output voltage reduces. FPGA 3s50 IC is affected during this contact discharge on the input pin. The DAC ICs are affected during the ESD discharge one due to direct ESD effects and the other due to indirect ESD effects. CPLD 9572 IC is also affected by ESD. Because of the ESD discharge in the surrounding and on the inp ut pin of the FPGA/CPLD kit, the ceramic capacitor in the SMPS power supply connected to the kit has shorted and found to be damaged. This is an after-effect observed after the ESD test. The damaged capacitor has been instrumental in contributing to the damage of the FPGA and CPLD ICs. Decapping of the FPGA and CPLD ICs confirmed the failure of these ICs due to ESD. The input/output pin bond pad and the metatop layer of FPGA 3s50 IC is damaged and there is dielectric breakdown observed in CPLD 9572 IC which makes these devices highly susceptible to ESD.Future ScopeMuch effort has been put into characterizing the effect and impact of ESD on individual ICs, on different designed circuits and few systems such as FPGA/CPLD kit, microcontroller units with various interfaces. However, less time has been spent in modeling all of these circuits/systems and to observe their behavior towards ESD using simulationtools. An effort in mathematical modeling and simulation has however been done wit h susceptibility of electronic system and cables due to radiated ESD fields. Also circuit modeling has been done for the analog circuits. The experimental based conducted susceptibility tests on various electronic components have resulted in some new results. Some of these results have reiterated some of the cognise facts and some results have given rise to new thoughts in implementing ESD protected circuit/system.ESD threat level variation to electronic components depends on the discharge voltage of ESD source, discharge point, structure and design of the component. ESD threat to components attach in systems may significantly vary from the threat to unmounted, individual components. New models need to be designed to predict the condition while the device is working in the system and using the computer simulations it is necessary to predict the ESD voltage, power and energy threats to system-mounted component. This is one area where the experimental results can be compared with th e simulated results and the source of the threat, the point of discharge and its impact on the system can be confirmed. Also new protection schemes can be adapted to make the system less susceptible to ESD.Another area of pertain where ESD tests can be conducted is in the area of high speed radio frequency (RF) circuits and systems. As the posit for wireless (RF) and high-speed mixed-signal systems continues to increase rapidly, providing sufficient ESD protection for these systems poses a major design and reliability challenge. This is due to the fact that in applying ESD protection to these systems, the protection system must be transparent the protection circuit must not affect the signal under normal operating conditions. A poorly designed protection system can generate impedance mismatches, causing reflections of signals, corruption of signal integrity, and inefficient power transfer between the signal pin and the core circuit. Broadband RF system protection because of ESD parasitical capacitance poses a greater challenge alternate protection schemes may be necessary. This necessitates us to beginning(a) understand effect of ESD on these high speed RF systems. However, there is little published data that provides performance analysis of RF circuits with various ESD protection design options scheme, which is attractive for operations in the multi-GHz regime.